FPGA Market

GAL20LV8D-5LJ

Lattice SPLD GAL

8 macrocells 28-pin

Available

The GAL20LV8D-5LJ is a Lattice SPLD GAL based on the GAL20LV8D device, with 8 macrocells. It comes in the LJ package (28-PLCC, 11.51 × 11.51 mm), speed grade 5.

Macrocells
8
Pins
28
Speed grade
5

Part details

Manufacturer
Lattice Semiconductor
Part number
GAL20LV8D-5LJ
Base device
GAL20LV8D
Family
SPLD GAL
Package
LJ
Pin / ball count
28
Speed grade
5

Device specifications

Specifications

Package outline
28-PLCC, 11.51 × 11.51 mm
Package / case
28-LCC (J-Lead)
Mounting
Surface Mount
Macrocells
8
Programming
EE PLD
Speed
5 ns

Part number breakdown

SegmentFieldMeaning
GAL20LV8DBase DeviceDevice GAL20LV8D
5Speed Grade5
LJPackageLJ

Frequently asked questions

What package is the GAL20LV8D-5LJ?
The GAL20LV8D-5LJ comes in the LJ package (28-PLCC, 11.51 × 11.51 mm).

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